1. Field
The disclosure relates to semiconductor device, control method of semiconductor device, and control information generating method for semiconductor device.
2. Description of Related Art
FIG. 13 shows a conventional semiconductor device system 100 disclosed in “Supply Voltage Adjustment Technique for Low Power Consumption and its Application to SOCs with Multiple Threshold Voltage CMOS,” 2006 Symposium on VLSI Circuits Digest of Technical Papers, by Hiroshi Okano et al. The semiconductor device system 100 is a system relating to a conventional adaptive voltage scaling. The relation between the frequency characteristic of a ring oscillator of a process sensor block 112 and the process variation value on the SPICE model used in simulation is tabulated, and an F-P table 131 is generated. Then, by simulating in plural conditions (by varying process and voltage), the relation between the process variation value and the power supply voltage is tabulated, and a P-V table 141 is generated. The method of simulation is, for example, a method of acquiring the relation between the process variation value and power supply voltage so as to obtain a set-up time in the critical path in the semiconductor device.
The power supply voltage to be supplied from a DC-DC converter 103 to a semiconductor device 102 is determined from the frequency characteristic by using the P-V table 141. As a result, according to the variation state in the manufacturing process of the semiconductor device 102, the value of the power supply voltage to be supplied from the DC converter 103 is determined.
A conventional technique is disclosed in Japanese Patent Application Laid-Open No. 2007-133497.
The conventional technique was, however, when projecting the process variation value to the performance of the transistor, based on two extreme conditions, that is, either all of the plural types of the process variation values are changed to the worst direction, or to the best direction. Indeed, all of the plural types of the process variation values are not fully changed to the worst direction or the best direction, and as far as the two extreme cases are considered, the process variation values is not fully projected onto the performance of the transistor. Hence, sufficient analysis precision is not obtained, and the design margin is set wider than required, and a higher power supply voltage than required is set, and therefore the power consumption of the semiconductor device 102 is not saved.
Also in the conventional technique, instead of evaluation in the two extreme conditions, if multiple conditions are analyzed in consideration of independent fluctuations of the plural types of the process variation values, each of the all possible combinations of the process variation values must be analyzed. Then a problem arises that such analysis requires a tremendous number of simulations, and the time and cost are increased so much.